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469 file number 3980.7 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hin200 thru hin213 +5v powered rs-232 transmitters/receivers with 0.1microfarad external capacitors the hin200-hin213 family of rs-232 transmitters/receivers interface circuits meet all ela rs-232e and v.28 specifications, and are particularly suited for those applications where 12v is not available. they require a single +5v power supply (except hin201 and hin209) and feature onboard charge pump voltage converters which generate +10v and -10v supplies from the 5v supply. the hin203 and hin205 require no external capacitors and are ideally suited for applications where circuit board space is critical. the family of devices offers a wide variety of rs-232 transmitter/receiver combinations to accommodate various applications (see selection table). the hin200, hin206, hin211 and hin213 feature a low power shutdown mode to conserve energy in battery powered applications. in addition, the hin213 provides two active receivers in shutdown mode allowing for easy wakeup capability. the drivers feature true ttl/cmos input compatibility, slew rate-limited output, and 300 w power-off source impedance. the receivers can handle up to 30v input, and have a 3k w to 7k w input impedance. the receivers also feature hysteresis to greatly improve noise rejection. applications ? any system requiring rs-232 communications port - computer - portable, mainframe, laptop - peripheral - printers and terminals - instrumentation - modems features ? meets all rs-232e and v.28 speci?cations ? hin203 and hin205 require no external capacitors ? requires only 0.1 m f or greater external capacitors ? 120kbit/s data rate ? two receivers active in shutdown mode (hin213) ? requires only single +5v power supply - (+5v and +12v - hin201 and hin209) ? onboard voltage doubler/inverter ? low power consumption (typ) . . . . . . . . . . . . . . . . . 5ma ? low power shutdown function (typ) . . . . . . . . . . . . 1 m a ? three-state ttl/cmos receiver outputs ? multiple drivers - 10v output swing for +5v lnput - 300 w power-off source impedance - output current limiting - ttl/cmos compatible - 30v/ m s maximum slew rate ? multiple receivers - 30v input voltage range -3k w to 7k w input impedance - 0.5v hysteresis to improve noise rejection selection table part number power supply voltage number of rs-232 drivers number of rs-232 receivers number of 0.1 m f external capacitors low power shutdown/ttl three-state number of receivers active in shutdown hin200 +5v 5 0 4 capacitors yes/no 0 hin201 +5v and +9v to 13.2v 2 2 2 capacitors no/no 0 hin202 +5v 2 2 4 capacitors no/no 0 hin203 +5v 2 2 none no/no 0 hin204 +5v 4 0 4 capacitors no/no 0 hin205 +5v 5 5 none yes/yes 0 hin206 +5v 4 3 4 capacitors yes/yes 0 hin207 +5v 5 3 4 capacitors no/no 0 hin208 5v 4 4 4 capacitors no/no 0 hin209 +5v and +9v to 13.2v 3 5 2 capacitors no/yes 0 hin211 +5v 4 5 4 capacitors yes/yes 0 hin213 +5v 4 5 4 capacitors yes/yes 2 data sheet february 1999 [ /title (hin2 00 thru hin21 3) /sub- ject (+5v pow- ered rs- 232 trans- mit- ters/re ceiv- ers with 0.1mic rofarad exter- nal capac- itors) /autho r () /key- words (inter- sil corpo- ration) /cre- ator () /doci nfo pdf- mark
470 ordering information part no. temp. range ( o c) package pkg. no. hin200cb 0 to 70 20 ld soic m20.3 hin200ib -40 to 85 20 ld soic m20.3 hin201cb 0 to 70 16 ld soic (w) m16.3 hin201ib -40 to 85 16 ld soic (w) m16.3 hin202cp 0 to 70 16 ld pdip e16.3 hin202cb 0 to 70 16 ld soic (w) m16.3 hin202ip -40 to 85 16 ld pdip e16.3 HIN202CA 0 to 70 16 ld ssop m16.209 hin202ia -40 to 85 16 ld ssop m16.209 hin202ib -40 to 85 16 ld soic (w) m16.3 hin202cbn 0 to 70 16 ld soic (n) m16.15 hin202ibn -40 to 85 16 ld soic (n) m16.15 hin203cp 0 to 70 20 ld pdip e20.3 hin203cb 0 to 70 20 ld soic (w) m20.3 hin204cb 0 to 70 16 ld soic (w) m16.3 hin204ib -40 to 85 16 ld soic (w) m16.3 hin205cp 0 to 70 24 ld pdip (w) e24.3 hin206cp 0 to 70 24 ld pdip (n) e24.3 hin206cb 0 to 70 24 ld soic m24.3 hin206ca 0 to 70 24 ld ssop m24.209 hin206ip -40 to 85 24 ld pdip (n) e24.3 hin206ib -40 to 85 24 ld soic m24.3 hin206ia -40 to 85 24 ld ssop m24.209 hin207cp 0 to 70 24 ld pdip (n) e24.3 hin207cb 0 to 70 24 ld soic m24.3 hin207ca 0 to 70 24 ld ssop m24.209 hin207ip -40 to 85 24 ld pdip (n) e24.3 hin207ib -40 to 85 24 ld soic m24.3 hin207ia -40 to 85 24 ld ssop m24.209 hin208cp 0 to 70 24 ld pdip (n) e24.3 hin208cb 0 to 70 24 ld soic m24.3 hin208ca 0 to 70 24 ld ssop m24.209 hin208ip -40 to 85 24 ld pdip (n) e24.3 hin208ib -40 to 85 24 ld soic m24.3 hin208ia -40 to 85 24 ld ssop m24.209 hin209cp 0 to 70 24 ld pdip (n) e24.3 hin209cb 0 to 70 24 ld soic m24.3 hin209ip -40 to 85 24 ld pdip (n) e24.3 hin209ib -40 to 85 24 ld soic m24.3 hin211cb 0 to 70 28 ld soic m28.3 hin211ca 0 to 70 28 ld ssop m28.209 hin211ib -40 to 85 28 ld soic m28.3 hin211ia -40 to 85 28 ld ssop m28.209 hin213cb 0 to 70 28 ld soic m28.3 hin213ca 0 to 70 28 ld ssop m28.209 hin213ib -40 to 85 28 ld soic m28.3 hin213ia -40 to 85 28 ld ssop m28.209 part no. temp. range ( o c) package pkg. no. pin descriptions pin function v cc power supply input 5v 10%, 5v 5% (hin200, hin207, hin203, and hin205). v+ internally generated positive supply (+10v nominal), hin201 and hin209 requires +9v to +13.2v. v- internally generated negative supply (-10v nominal). gnd ground lead. connect to 0v. c1+ external capacitor (+ terminal) is connected to this lead. c1- external capacitor (- terminal) is connected to this lead. c2+ external capacitor (+ terminal) is connected to this lead. c2- external capacitor (- terminal) is connected to this lead. t in transmitter inputs. these leads accept ttl/cmos levels. an internal 400k w pull-up resistor to v cc is connected to each lead. t out transmitter outputs. these are rs-232 levels (nominally 10v). r in receiver inputs. these inputs accept rs-232 input levels. an internal 5k w pull-down resistor to gnd is connected to each input. r out receiver outputs. these are ttl/cmos levels. en, en enable input. this is an active low input which enables the receiver outputs. with en = 5v, (hin213 en = 0v), the outputs are placed in a high impedance state. sd, sd shutdown input. with sd = 5v (hin213 sd = 0v), the charge pump is disabled, the receiver outputs are in a high impedance state (except r4 and r5 of hin213) and the transmitters are shut off. nc no connect. no connections are made to these leads. hin200 thru hin213
471 pinouts hin200 (soic) top view hin201 (soic) top view t3out t1out t2out t2in t1in gnd c1+ v cc v+ c1- t4out nc sd t5out t5in t4in t3in v- c2- c2+ 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c+ c- v- t2 out r2 in nc t2 in v+ gnd t1 out r1 in r1 out t1 in nc v cc r2 out v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t5 out t5 in t4 in t1 in t2 in t3 in t1 t2 t3 t4 t5 +5v 400k w +5v + 0.1 m f + 0.1 m f + 0.1 m f 5 4 2 3 14 1 15 20 16 19 8 10 9 13 v+ v- c1+ c1- c2+ c2- 17 sd 7 +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 11 12 gnd 6 v cc +5v 16 v+ +9v to +13.2v 15 t1 out t2 out t1 in t2 in t1 t2 10 7 13 4 +5v 400k w +5v 400k w r1 out r1 in r1 12 11 5k w r2 out r2 in r2 5 6 5k w +12v to -12v voltage inverter 0.1 m f 3 v- c+ c- + 0.1 m f 1 2 + gnd 14 hin200 thru hin213
472 hin202 (pdip, soic, ssop) top view hin203 (pdip, soic) top view pinouts (continued) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd v- 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 t2 in t1 in r1 out r1 in t1 out gnd (v+) c1+ v cc gnd (v-) c2- r2 out t2 out v- c2- r2 in c2+ v+ (c1-) c1- (c1+) v- (c2+) c2+ (c2-) note: pin numbers in parentheses are for soic package. v cc +5v 2 v+ 16 t1 out t2 out t1 in t2 in t1 t2 11 10 14 7 +5v 400k w +5v 400k w r1 out r1 in r1 13 12 5k w r2 out r2 in r2 8 9 5k w +10v to -10v voltage inverter 0.1 m f 6 v- c2+ c2- + 0.1 m f 4 5 +5v to 10v voltage inverter c1+ c1- + 0.1 m f 1 3 + 0.1 m f + gnd 15 6 v cc t1 out t2 out r1 out r2 in t1 in t2 in r1 in t1 +5v + 0.1 m f 4 5 1 2 18 14 (8) 19 8 (13) 12 (10) v+ v- c1+ c1- c2+ c2- +5v 400k w gnd 9 gnd 17 r2 out no connect internal -10v supply internal +10v supply v- c2+ c2- 13 (14) 5k w 6 20 11 (12) 15 16 10 (11) 3 t2 +5v 400k w 5k w hin200 thru hin213
473 hin204 (soic) top view hin205 (pdip) top view pinouts (continued) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 t1 out t2 out t2 in t1 in gnd v+ c1+ t3 out t4 in t3 in v- c2- c2+ c1- t4 out v cc 1 2 3 4 5 6 7 8 9 10 11 12 t4 out t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc 16 17 18 19 20 21 22 23 24 15 14 13 r3 in t5 in sd en t5 out r4 out t3 in r5 out r5 in r3 out r4 in t4 in 6 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 0.1 m f + 0.1 m f + 0.1 m f 4 3 1 2 13 16 14 15 7 9 8 12 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 10 11 gnd 5 12 v cc t1 out t1 in t1 +5v + 0.1 m f 6 2 3 18 1 19 24 10 400k w 13 14 r1 out r1 in r1 4 5 r2 out r2 in r2 23 22 r3 out r3 in r3 16 17 21 20 +5v t2 out t2 in +5v t3 out t3 in +5v t4 out t4 in +5v t5 out t5 in +5v 400k w 400k w 400k w 400k w t2 t3 t4 t5 gnd 9 r4 in r5 in r4 r5 11 15 7 8 r4 out r5 out en sd 5k w 5k w 5k w 5k w 5k w hin200 thru hin213
474 hin206 (pdip, soic, ssop) top view hin207 (pdip, soic, ssop) top view pinouts (continued) t3 out t1 out t2 out r1 in r1 out t2 in t1 in gnd v cc c1+ v+ c1- t4 out r2 out sd en t4 in r3 out v- c2- c2+ r2 in t3 in r3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 t3 out t1 out t2 out r1 in r1 out t2 in t1 in gnd v cc c1+ v+ c1- t4 out r2 out t5 in t5 out t4 in r3 out v- c2- c2+ r2 in t3 in r3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 0.1 m f + 0.1 m f + 0.1 m f 7 6 2 3 18 1 19 24 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 13 14 r1 out r1 in r1 4 5 5k w r2 out r2 in r2 23 22 5k w r3 out r3 in r3 16 17 5k w en 20 21 sd gnd 8 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 0.1 m f + 0.1 m f + 0.1 m f 7 6 2 3 18 1 19 24 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 13 14 r1 out r1 in r1 4 5 5k w r2 out r2 in r2 23 22 5k w r3 out r3 in r3 16 17 5k w t5 out t5 in t5 21 20 +5v 400k w gnd 8 hin200 thru hin213
475 hin208 (pdip, soic, ssop) top view hin209 (pdip, soic, ssop) top view pinouts (continued) t2 out t1 out r2 in r2 out t1 in r1 out r1 in gnd v cc c1+ v+ c1- t3 out r3 out t4 in t4 out t3 in r4 out v- c2- c2+ r3 in t2 in r4 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 r1 out r1 in gnd v cc v+ c1+ c1- v- r5 in r5 out r4 out r4 in t1 in r2 out r2 in t2 out t1 out r3 out nc* en t3 out t2 in r3 in t3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 0.1 m f + 0.1 m f + 0.1 m f 5 18 2 1 19 24 21 20 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 13 14 r1 out r1 in r1 7 6 5k w r2 out r2 in r2 3 4 5k w r3 out r3 in r3 23 22 5k w r4 out r4 in r4 16 17 5k w gnd 8 4 v cc +12v to -12v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 0.1 m f + 0.1 m f 24 23 19 20 16 13 6 7 5 8 v+ c1+ c1- +5v 400k w +5v 400k w +5v 400k w r1 out r1 in r1 2 5k w r2 out r2 in r2 21 22 5k w r3 out r3 in r3 18 17 5k w r4 out r4 in r4 12 11 5k w r5 out r5 in r5 9 10 5k w en 14 1 +9v to +13.2v v- gnd 3 hin200 thru hin213
476 hin211 (soic, ssop) top view hin213 (soic, ssop) top view pinouts (continued) t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc c1+ v+ c1- t4 out r3 out sd en r4 in t4 in r5 out r5 in v- c2- c2+ r3 in r4 out t3 in 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc c1+ v+ c1- t4 out r3 out sd en r4 in t4 in r5 out r5 in v- c2- c2+ r3 in r4 out t3 in 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 note: r4 and r5 active in shutdown 11 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 0.1 m f + 0.1 m f + 0.1 m f 7 6 2 3 20 1 12 14 13 17 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 15 16 r1 out r1 in r1 9 5k w r2 out r2 in r2 4 5 5k w r3 out r3 in r3 27 26 5k w r4 out r4 in r4 23 22 5k w r5 out r5 in r5 18 19 5k w en 24 8 t4 out t4 in t4 21 28 +5v 400k w sd 25 gnd 10 11 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 0.1 m f + 0.1 m f + 0.1 m f 7 6 2 3 20 1 12 14 13 17 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w + 0.1 m f 15 16 r1 out r1 in r1 9 5k w r2 out r2 in r2 4 5 5k w r3 out r3 in r3 27 26 5k w r4 out r4 in r4 23 22 5k w r5 out r5 in r5 18 19 5k w en 24 8 t4 out t4 in t4 21 28 +5v 400k w 25 sd gnd 10 hin200 thru hin213
477 absolute maximum ratings thermal information v cc to ground. . . . . . . . . . . . . . . . . . . . . . (gnd -0.3v) 478 ttl/cmos receiver output voltage low, v ol i out = 1.6ma (hin201-hin203, i out = 3.2ma) - 0.1 0.4 v ttl/cmos receiver output voltage high, v oh i out = -1ma 3.5 4.6 - v output enable time, t en hin205, hin206, hin209, hin211, hin213 - 400 - ns output disable time, t dis hin205, hin206, hin209, hin211, hin213 - 200 - ns transmit, receive propagation delay, t pd hin213 sd = 0v, r4, r5 - 0.5 40 m s hin213 sd = v cc , r1 - r5 - 0.5 10 m s hin200 - hin211 - 0.5 10 m s transmit transition region slew rate, sr t r l = 3k w , c l = 2500pf measured from +3v to -3v or -3v to +3v (note 2) hin200, hin204 to hin211, hin213 3 - 30 v/ m s hin201, hin202, hin203 3 - 30 v/ m s output resistance, r out v cc = v+ = v- = 0v, v out = 2v 300 - - w rs-232 output short circuit current, i sc t out shorted to gnd - 10 - ma ttl/cmos receiver output leakage en = v cc , en = 0, 0v < r out < v cc - 0.05 10 m a note: 2. guaranteed by design. electrical speci?cations test conditions: v cc = +5v 10%, (v cc = +5v 5% hin200, hin203, hin205, hin207); v+ = 9v to 13.2v, hin201 and hin209), c1-c4 = 0.1 m f; t a = operating temperature range (continued) parameter test conditions min typ max units + - c1 + - c3 + - c2 + - c4 s1 s2 s5 s6 s3 s4 s7 s8 v cc gnd rc oscillator v cc gnd v+ = 2v cc gnd v - = - (v+) c1+ c1 - c2 - c2+ voltage inverter voltage doubler figure 1. charge pump hin200 thru hin213
479 detailed description the hin200 thru hin213 family of rs-232 transmitters/receivers are powered by a single +5v power supply (except hin201 and hin209), feature low power consumption, and meet all ela rs232c and v.28 specifications. the circuit is divided into three sections: the charge pump, transmitter, and receiver. charge pump an equivalent circuit of the charge pump is illustrated in figure 1. the charge pump contains two sections: the voltage doubler and the voltage inverter. each section is driven by a two phase, internally generated clock to generate +10v and - 10v. the nominal clock frequency is 125khz. during phase one of the clock, capacitor c1 is charged to v cc . during phase two, the voltage on c1 is added to v cc , producing a signal across c3 equal to twice v cc . during phase two, c2 is also charged to 2v cc , and then during phase one, it is inverted with respect to ground to produce a signal across c4 equal to -2v cc . the charge pump accepts input voltages up to 5.5v. the output impedance of the voltage doubler section (v+) is approximately 200 w , and the output impedance of the voltage inverter section (v-) is approximately 450 w . a typical application uses 0.1 m f capacitors for c1-c4, however, the value is not critical. increasing the values of c1 and c2 will lower the output impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, c3 and c4, lowers the ripple on the v+ and v- supplies. during shutdown mode (hin200, hin206 and hin211, sd=v cc , hin213, sd = 0v) the charge pump is turned off, v+ is pulled down to v cc , v- is pulled up to gnd, and the supply current is reduced to less than 10 m a. the transmitter outputs are disabled and the receiver outputs (except for hin213, r4 and r5) are placed in the high impedance state. transmitters the transmitters are ttl/cmos compatible inverters which translate the inputs to rs-232 outputs. the input logic threshold is about 26% of v cc , or 1.3v for v cc = 5v. a logic 1 at the input results in a voltage of between -5v and v- at the output, and a logic 0 results in a voltage between +5v and (v+ - 0.6v). each transmitter input has an internal 400k w pullup resistor so any unused input can be left unconnected and its output remains in its low state. the output voltage swing meets the rs-232c specifications of 5v minimum with the worst case conditions of: all transmitters driving 3k w minimum load impedance, v cc = 4.5v, and maximum allowable operating temperature. the transmitters have an internally limited output slew rate which is less than 30v/ m s. the outputs are short circuit protected and can be shorted to ground indefinitely. the powered down output impedance is a minimum of 300 w with 2v applied to the outputs and v cc = 0v. receivers the receiver inputs accept up to 30v while presenting the required 3k w to 7k w input impedance even if the power is off (v cc = 0v). the receivers have a typical input threshold of 1.3v which is within the 3v limits, known as the transition region, of the rs-232 speci?cations. the receiver output is 0v to v cc . the output will be low whenever the input is greater than 2.4v and high whenever the input is ?oating or driven between +0.8v and -30v. the receivers feature 0.5v hysteresis (except during shutdown) to improve noise rejection. the receiver enable line ( en, on hin206, hin209, and hin211, en on hin213) when unasserted, disables the receiver outputs, placing them in the high impedance mode. the receiver outputs are also placed in the high impedance state when in shutdown mode (except hin213 r4 and r5). hin213 operation in shutdown the hin213 features two receivers, r4 and r5, which remain active in shutdown mode. during normal operation the receivers propagation delay is typically 0.5 m s. this propagation delay may increase slightly during shutdown. when entering shut down mode, receivers r4 and r5 are not valid for 80 m s after sd = v il . when exiting shutdown mode, all receiver outputs will be invalid until the charge pump circuitry reaches normal operating voltage. this is typically less than 2ms when using 0.1 m f capacitors. t out v- < v tout < v+ 300 w 400k w t xin gnd < t xin < v cc v- v+ v cc figure 2. transmitter r out gnd < v rout < v cc 5k w r xin -30v < r xin < +30v gnd v cc figure 3. receiver t in v ol v ol t plh t phl average propagation delay = t phl + t plh 2 or r in t out or r out figure 4. propagation delay definition hin200 thru hin213
480 application information the hinxxx may be used for all rs-232 data terminal and communication links. it is particularly useful in applications where 12v power supplies are not available for conventional rs-232 interface circuits. the applications presented represent typical interface con?gurations. a simple duplex rs-232 port with cts/rts handshaking is illustrated in figure 9. fixed output signals such as dtr (data terminal ready) and dsrs (data signaling rate select) is generated by driving them through a 5k w resistor connected to v+. in applications requiring four rs-232 inputs and outputs (figure 10), note that each circuit requires two charge pump capacitors (c1 and c2) but can share common reservoir capacitors (c3 and c4). the bene?t of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. typical performance curves figure 5. v- supply voltage vs v cc figure 6. v+, v- output voltage vs load 12 10 8 6 4 2 0 3.5 4.0 4.5 6.0 v cc v- supply voltage (v) 5.0 5.5 3.0 0.1 m f 35 |i load | (ma) v+ (v cc = 4v) v+ (v cc = 5v) v- (v cc = 5v) v- (v cc = 4v) t a = 25 o c transmitter outputs open circuit 30 25 20 15 10 5 0 supply voltage (|v|) 0 12 10 8 6 4 2 test circuits (hin202) figure 7. general test circuit figure 8. po wer-off source resistance configuration 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd +4.5v to +5.5v input 3k w t1 output rs-232 30v input ttl/cmos output ttl/cmos input ttl/cmos input ttl/cmos output + - 0.1 m f c3 + - 0.1 m f c1 + - 0.1 m f c2 + - 0.1 m f c4 3k w output rs-232 30v input t2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd t2 out t1 out v in = 2v a r out = v in /i hin200 thru hin213
481 - + - + - + ctr (20) data terminal ready dsrs (24) data signaling rate rs-232 inputs and outputs td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send signal ground (7) 15 8 13 7 14 16 - + 6 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin202 c1 0.1 m f c2 0.1 m f td rts rd cts select +5v inputs outputs ttl/cmos figure 9. simple duplex rs-232 port with cts/rts handshaking - + rs-232 inputs and outputs dtr (20) data terminal ready dsrs (24) data signaling rate select dcd (8) data carrier detect r1 (22) ring indicator signal ground (7) 15 8 13 7 14 2 - + 4 r2 r1 t2 t1 9 12 10 11 3 1 hin202 c1 0.1 m f dtr dsrs dcd r1 +5v inputs outputs ttl/cmos - + - + td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send 8 13 7 14 15 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin202 c1 0.1 m f c2 0.1 m f td rts rd cts inputs outputs ttl/cmos - + 5 c2 0.1 m f 16 c3 0.2 m f 6 2 6 v- v+ - + c4 0.2 m f 16 v cc v cc figure 10. combining two hin202s for 4 pairs of rs-232 inputs and outputs hin200 thru hin213
482 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 die characteristics die dimensions: 160 mils x 140 mils metallization: type: al thickness: 10k ? 1k ? substrate potential v+ passivation: type: nitride over silox nitride thickness: 8k ? silox thickness: 7k ? transistor count: 238 process: cmos metal gate metallization mask layout hin211 t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc c1+ v+ c1- c2+ c2- v- r5 in r5 out t3 in t4 in r4 out r4 in en shd t4 out r3 in r3 out hin200 thru hin213

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